1. Field of the Invention
The present invention relates to an integrated structure active clamp for the protection of power semiconductor devices, such as power MOSFETs, IGBTs or power BJTs, against overvoltages.
2. Discussion of the Related Art
Dynamic clamp circuits are generally used in conjunction with power semiconductor devices, which drive inductive loads, to protect the power devices against overvoltages which are generated when the load current is switched off.
Dynamic clamp circuits are divided into two broad categories: active and passive clamp circuits.
A typical active clamp circuit comprises two zener diodes connected by their anodes, and a resistor. A first or reverse zener diode has its cathode connected to a terminal of the power device to which the inductive load is also connected, for example a drain terminal of a power MOSFET, a collector terminal of an Insulated Gate Bipolar Transistor (IGBT) or a collector terminal of a power Bipolar Junction Transistor (power BJT). A second or forward zener diode has its cathode connected to a driving electrode of the power device, i.e. the gate electrode of a power MOSFET, the gate electrode of an IGBT or the base electrode of a power BJT. The resistor is connected between the driving electrode of the power device and a driving terminal to which a driving signal is applied.
The operation of the circuit will now be explained referring for example to a power MOSFET. When the driving terminal is driven low, the power MOSFET is turned off. Due to the inductive nature of the load, an overvoltage appears on the drain terminal. If the zener voltage Vz of the first zener diode is lower than the breakdown voltage of the power MOSFET, when the voltage on the drain terminal exceeds Vz (more precisely, when the drain voltage exceeds Vz plus the forward voltage necessary to turn the second zener diode on), the first zener diode breaks down, and an electrical current flows through the two zener diodes and the resistor to the driving terminal. This current gives rise to a voltage drop across the resistor, thus raising the voltage on the gate terminal of the power MOSFET, which causes the power MOSFET to turn on again, so that the overvoltage is limited. The second zener diode is used to prevent current from flowing from the driving terminal to the drain terminal when the driving terminal is driven high (i.e. when the power device is switched on), so that a full 5 V signal can be applied to the gate electrode of the power MOSFET.
A clamp circuit such that described works better if it is integrated in the same chip of the power semiconductor device; in this case parasitic inductances are greatly reduced, as well as the operating times of the clamp circuit.
JP-A-4065878 (corresponding to U.S. Pat. No. 5,162,966) describes an active clamp circuit, which is suitable for being integrated in power MOSFET chips and is conceptually identical to the circuit described above, the only difference being a chain of serially connected first zener diodes instead of the single first zener diode. Each first zener diode has an anode region constituted by a P+ semiconductor region, obtained simultaneously with the deep body regions of the various elementary cells of the power MOSFET, and a cathode region constituted by an N+ semiconductor region also obtained within the anode region simultaneously with the source regions of the power MOSFET. The second zener diode has the cathode region connected to the gate electrode of the power device by means of a metal layer and the anode region connected to the anode region of an adjacent one of the first diodes. A cathode region of the last one of the series of first zener diodes is connected to the drain of the power MOSFET by means of an N+ contact region disposed on an Nepitaxial layer (also called "drift layer") which is grown over an N+ substrate and in which the elementary cells of the power device are also obtained.
When however such a structure is integrated in a power device, the breakdown voltage of the overall device is lower than the breakdown voltage of the power device alone, due to the presence of parasitic bipolar transistors, associated with each of the zener diodes, having emitter and base represented by the N+ cathode regions and by the P+ anode regions of the zener diodes, and collector represented by the Ndrift layer. When the power device is switched off, its gate and source are at the same potential, while the cathode region of the last zener diode of the chain of first zener diodes is at the same potential as the drain electrode of the power MOSFET; in such conditions, the breakdown voltage of the overall device is equal to the collector to emitter breakdown voltage (BVCEO) of the parasitic transistor. The breakdown voltage of the power MOSFET alone is given by the breakdown voltage of the junction between the deep body regions and the drift layer (BV CBO), since in each elementary cell of the power MOSFET the source and the deep body regions are short-circuited. Since the emitter to collector breakdown voltage is: EQU BV.sub.CEO =BV.sub.CBO /.sqroot.h.sub.FE
it appears that the breakdown voltage of the chip is greatly reduced with respect to the breakdown voltage of the power MOSFET taken alone.
Another disadvantage of this structure is that, since both the anode and cathode regions of the zener diodes are heavily doped semiconductor regions, the breakdown voltage of each diode is low. On the one hand, the low breakdown voltage makes it necessary to connect in series a certain number of diodes if a relatively high clamping voltage is to be attained. On the other hand, the low breakdown voltage limits the maximum voltage value of the driving signal which can be applied to the driving terminal of the power device without causing the zener diode which has the cathode connected to the gate electrode of the power device to break down when the power device is switched on.
In Japanese Application JP-A-055202 (corresponding to U.S. Pat. No. 5,221,850), an active clamp structure is disclosed comprising a silicon junction diode and a polysilicon junction diode, connected in series. The polysilicon diode has the cathode connected to the gate of the power MOSFET; the silicon diode has an anode comprising a deep P+ region which is deeper than the P+ deep body regions of the elementary cells, and the cathode is connected to the drain of the power MOSFET through the Ndrift layer. Since the junction of the silicon diode is deeper than the junction between the deep body regions of the cells and the drift layer, the breakdown voltage of the silicon diode is lower than that of the power MOSFET as is desired, and a clamping action is therefore achieved.
This structure has two advantages with respect to the previous one. First, it is more compact, since it is not necessary to have a chain of series diodes. Second, since the polysilicon diode is fabricated in a polysilicon layer deposited over an insulating oxide layer, it is electrically isolated from the Ndrift layer and thus from the drain of the power MOSFET, and no parasitic transistors are therefore formed. The overall breakdown voltage is therefore not reduced as was the case with the previous described structure.
The main disadvantage of this structure resides in that the breakdown voltage of the silicon diode (i.e. the clamping voltage of the active clamp) depends on the thickness of the drift layer under the anode region of the diode. Since the drift layer is normally an epitaxial layer, its resistivity and thickness vary from wafer to wafer and from lot to lot, and the value of the clamping voltage is therefore variable. Another disadvantage is given by the long diffusion time required to obtain the deep anode region of the silicon diode; this causes the doping concentration profile of the drain of the MOSFET to vary.